The present invention relates to a layout analysis method and apparatus for analyzing systematic variations in a semiconductor integrated circuit and generating a physical parameter distribution that depends on the layout.
Large-scale integrated circuits (LSIs) have increasingly been miniaturized in recent years. For such miniaturized LSIs, variations in layout patterns and arrangements of circuit elements or variations in manufacturing processes greatly affect circuit performance. Systematic variations (variations for which cause can be identified using design data) cannot be distinguished from random variations (variations for which cause cannot be identified using design data) in present LSI design environments. Thus, circuits employ worst-case designs, which take into consideration all possible variations and include excessive margins for overcoming the worst conditions. In recent years, LSIs are required to operate at a lower voltage to reduce power consumption and operate at higher speeds. However, circuits with excessive margins hinder reduction in power consumption and increase in operation speed. Moreover, it is difficult to provide sufficient margins. To enable circuit designing with reduced margins, it is necessary to analyze systematic variations for a semiconductor integrated circuit and generate a physical parameter distribution that depends on the layout.
FIG. 1 shows a transistor layout on a chip 1. The transistor is formed with poly gates 3 and diffusion regions 2. In a miniaturized LSI, transistor characteristics change greatly in accordance with differences in transistor pattern shapes and density (interval) and positions of poly gates.
For example, the intervals of the poly gates 3 differ between transistors formed in areas a, b, and c. This is the same in areas d, e, and f. The transistors formed in areas a and d have the same pattern. However, since the transistors in areas a and d are located at different positions and arranged in different orientations, the transistor characteristics in area a and area d are different.
Under present designing environments, there are no analyzing means or processes for locating causes of processing variations. Thus, characteristics, such as delay time, power consumption, and leakage current, are analyzed using transistor characteristics under the worst condition (worst point) and best condition (best point) as parameters for characteristic analysis.